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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-28 01:06:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-09-28 01:10:10 -0700 |
| commit | 55c66198fd6bc8f1b16e67a33d2865ca3e7269cb (patch) | |
| tree | ce99f060a7d7024ffbda6bc1c4c5487c925a346b /riscv | |
| parent | 1c227a1d3b5802b5bc01ce2dfd4377f35db1800e (diff) | |
| download | spike-55c66198fd6bc8f1b16e67a33d2865ca3e7269cb.zip spike-55c66198fd6bc8f1b16e67a33d2865ca3e7269cb.tar.gz spike-55c66198fd6bc8f1b16e67a33d2865ca3e7269cb.tar.bz2 | |
Fix vmv.x.s for RV32
The Spike internals require that, when XLEN is narrower than reg_t,
values be sign-extended to the width of reg_t.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/vmv_x_s.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 8451d6a..16153eb 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -1,27 +1,28 @@ // vmv_x_s: rd = vs2[0] require_vector(true); require(insn.v_vm() == 1); -uint64_t xmask = UINT64_MAX >> (64 - P.get_isa().get_max_xlen()); reg_t rs1 = RS1; reg_t sew = P.VU.vsew; reg_t rs2_num = insn.rs2(); +reg_t res; switch (sew) { case e8: - WRITE_RD(P.VU.elt<int8_t>(rs2_num, 0)); + res = P.VU.elt<int8_t>(rs2_num, 0); break; case e16: - WRITE_RD(P.VU.elt<int16_t>(rs2_num, 0)); + res = P.VU.elt<int16_t>(rs2_num, 0); break; case e32: - WRITE_RD(P.VU.elt<int32_t>(rs2_num, 0)); + res = P.VU.elt<int32_t>(rs2_num, 0); break; case e64: - if (P.get_isa().get_max_xlen() <= sew) - WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0) & xmask); - else - WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0)); + res = P.VU.elt<uint64_t>(rs2_num, 0); break; +default: + abort(); } +WRITE_RD(sext_xlen(res)); + P.VU.vstart->write(0); |