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| author | Udit Khanna <udit.khanna@sifive.com> | 2020-05-12 00:37:50 -0700 |
|---|---|---|
| committer | Udit Khanna <udit.khanna@sifive.com> | 2020-05-12 00:37:50 -0700 |
| commit | 47026a2119456b3e431b30dfcaeb6fa9829b438b (patch) | |
| tree | 8ee363d74dd5c9612e9c0f404be26cdd2ffd6d39 /riscv | |
| parent | 9430a823731b068c16972f5d790c55661e183acf (diff) | |
| download | spike-47026a2119456b3e431b30dfcaeb6fa9829b438b.zip spike-47026a2119456b3e431b30dfcaeb6fa9829b438b.tar.gz spike-47026a2119456b3e431b30dfcaeb6fa9829b438b.tar.bz2 | |
Hardwire mstatus.[sie,spie] to zero if 'S' mode absent
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 2dc930b..72f2c92 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -697,9 +697,8 @@ void processor_t::set_csr(int which, reg_t val) || supports_extension('V'); bool has_vs = supports_extension('V'); - reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_MPRV - | (supports_extension('S') ? MSTATUS_SUM : 0) + reg_t mask = MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV + | (supports_extension('S') ? (MSTATUS_SUM | MSTATUS_SIE | MSTATUS_SPIE) : 0) | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM | MSTATUS_TSR | (has_fs ? MSTATUS_FS : 0) | (has_vs ? MSTATUS_VS : 0) |