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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 00:03:17 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 21:24:19 -0700 |
| commit | 3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915 (patch) | |
| tree | d6d0d7aa29cc5966c3afead8b21e3bca5c9cb1ee /riscv | |
| parent | 0884e5bbd77a4df950c2ccfff78ad157ffcec631 (diff) | |
| download | spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.zip spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.gz spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.bz2 | |
commitlog: extend hint bit to record csr access
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 8 | ||||
| -rw-r--r-- | riscv/execute.cc | 8 | ||||
| -rw-r--r-- | riscv/processor.h | 2 |
3 files changed, 12 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 71caa58..34fa1d2 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -180,16 +180,18 @@ private: #else /* 0 : int * 1 : floating - * 2 : vector + * 2 : vector reg + * 3 : vector hint + * 4 : csr */ # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects */ \ - STATE.log_reg_write[(reg) << 2] = {wdata, 0}; \ + STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ freg_t wdata = freg(value); /* value may have side effects */ \ - STATE.log_reg_write[((reg) << 2) | 1] = wdata; \ + STATE.log_reg_write[((reg) << 4) | 1] = wdata; \ DO_WRITE_FREG(reg, wdata); \ }) # define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; diff --git a/riscv/execute.cc b/riscv/execute.cc index 7e89cd1..45fa516 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -81,10 +81,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) char prefix; int size; - int rd = item.first >> 2; + int rd = item.first >> 4; bool is_vec = false; bool is_vreg = false; - switch (item.first & 3) { + switch (item.first & 0xf) { case 0: size = xlen; prefix = 'x'; @@ -101,6 +101,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) case 3: is_vec = true; break; + case 4: + size = xlen; + prefix = 'c'; + break; default: assert("can't been here" && 0); break; diff --git a/riscv/processor.h b/riscv/processor.h index 676a52d..68e13d8 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -481,7 +481,7 @@ public: #ifdef RISCV_ENABLE_COMMITLOG if (is_write) - p->get_state()->log_reg_write[((vReg) << 2) | 2] = {0, 0}; + p->get_state()->log_reg_write[((vReg) << 4) | 2] = {0, 0}; #endif T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3)); |