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| author | Andrew Waterman <andrew@sifive.com> | 2017-06-07 14:17:58 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-06-07 15:04:34 -0700 |
| commit | 3e92055f8323729fdfa72e4ac463ed677424606c (patch) | |
| tree | 1c11f81e8d606e931d6755ac96513a8bdf5fcfa8 /riscv | |
| parent | ea6768d281b8c56056b04ecc5cc11380cb4fa178 (diff) | |
| download | spike-3e92055f8323729fdfa72e4ac463ed677424606c.zip spike-3e92055f8323729fdfa72e4ac463ed677424606c.tar.gz spike-3e92055f8323729fdfa72e4ac463ed677424606c.tar.bz2 | |
Forbid S-mode execution from user memory
https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 76a6ab1..54b5b1d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -163,7 +163,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) if (vm.levels == 0) return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen - bool supervisor = mode == PRV_S; + bool s_mode = mode == PRV_S; bool sum = get_field(proc->state.mstatus, MSTATUS_SUM); bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR); @@ -189,7 +189,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) if (PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; - } else if ((pte & PTE_U) ? supervisor && !sum : !supervisor) { + } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { break; } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { break; |