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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-04-04 17:25:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-04-04 17:25:01 -0700 |
| commit | 2dbcb01ca1c026b867cf673203646d213f6e6b5c (patch) | |
| tree | 9154e72b3b3aee68294b456c559bea7e05fa21f0 /riscv | |
| parent | 4856220f05094a870e9544523428b85ec597fd42 (diff) | |
| download | spike-2dbcb01ca1c026b867cf673203646d213f6e6b5c.zip spike-2dbcb01ca1c026b867cf673203646d213f6e6b5c.tar.gz spike-2dbcb01ca1c026b867cf673203646d213f6e6b5c.tar.bz2 | |
Allow querying the mmu configuration chosen during the build. (#191)
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index f0bc19d..a3f06c6 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -239,6 +239,24 @@ public: void register_memtracer(memtracer_t*); + int is_dirty_enabled() + { +#ifdef RISCV_ENABLE_DIRTY + return 1; +#else + return 0; +#endif + } + + int is_misaligned_enabled() + { +#ifdef RISCV_ENABLE_MISALIGNED + return 1; +#else + return 0; +#endif + } + private: simif_t* sim; processor_t* proc; |