diff options
author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:33:25 -0700 |
---|---|---|
committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:46:06 -0700 |
commit | 29d89ec1e6c771b49f6f7e3bf225fcb46990f8ed (patch) | |
tree | adf15f48976476fb6f1d312769472a2d4fa93d97 /riscv | |
parent | eb601cb5320103c3ddcc1e71549bc9b1a8038c6f (diff) | |
download | spike-29d89ec1e6c771b49f6f7e3bf225fcb46990f8ed.zip spike-29d89ec1e6c771b49f6f7e3bf225fcb46990f8ed.tar.gz spike-29d89ec1e6c771b49f6f7e3bf225fcb46990f8ed.tar.bz2 |
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/execute.h | 414 | ||||
-rw-r--r-- | riscv/insns/fmovn.h (renamed from riscv/insns/fldseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fmovz.h (renamed from riscv/insns/fldsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/movn.h (renamed from riscv/insns/flwseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/movz.h (renamed from riscv/insns/flwsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfld.h (renamed from riscv/insns/fld_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflsegd.h (renamed from riscv/insns/fsdseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflsegstd.h (renamed from riscv/insns/fsdsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflsegstw.h (renamed from riscv/insns/fswseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflsegw.h (renamed from riscv/insns/fswsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflstd.h (renamed from riscv/insns/fldst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflstw.h (renamed from riscv/insns/flwst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vflw.h (renamed from riscv/insns/flw_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfmst.h (renamed from riscv/insns/fmov_su.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfmsv.h (renamed from riscv/insns/fmov_sv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfmts.h (renamed from riscv/insns/fmov_us.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfmvv.h (renamed from riscv/insns/fmov_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfsd.h (renamed from riscv/insns/fsd_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfssegd.h (renamed from riscv/insns/lbseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfssegstd.h (renamed from riscv/insns/lbsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfssegstw.h (renamed from riscv/insns/lbuseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfssegw.h (renamed from riscv/insns/lbusegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfsstd.h (renamed from riscv/insns/fsdst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfsstw.h (renamed from riscv/insns/fswst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfsw.h (renamed from riscv/insns/fsw_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlb.h (renamed from riscv/insns/lb_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlbu.h (renamed from riscv/insns/lbu_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vld.h (renamed from riscv/insns/ld_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlh.h (renamed from riscv/insns/lh_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlhu.h (renamed from riscv/insns/lhu_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegb.h (renamed from riscv/insns/ldseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegbu.h (renamed from riscv/insns/ldsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegd.h (renamed from riscv/insns/lhseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegh.h (renamed from riscv/insns/lhsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlseghu.h (renamed from riscv/insns/lhuseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegstb.h (renamed from riscv/insns/lhusegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegstbu.h (renamed from riscv/insns/lwseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegstd.h (renamed from riscv/insns/lwsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegsth.h (renamed from riscv/insns/lwuseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegsthu.h (renamed from riscv/insns/lwusegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegstw.h (renamed from riscv/insns/sbseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegstwu.h (renamed from riscv/insns/sbsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegw.h (renamed from riscv/insns/sdseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsegwu.h (renamed from riscv/insns/sdsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlstb.h (renamed from riscv/insns/lbst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlstbu.h (renamed from riscv/insns/lbust_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlstd.h (renamed from riscv/insns/ldst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsth.h (renamed from riscv/insns/lhst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlsthu.h (renamed from riscv/insns/lhust_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlstw.h (renamed from riscv/insns/lwst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlstwu.h (renamed from riscv/insns/lwust_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlw.h (renamed from riscv/insns/lw_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vlwu.h (renamed from riscv/insns/lwu_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vmst.h (renamed from riscv/insns/mov_su.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vmsv.h (renamed from riscv/insns/mov_sv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vmts.h (renamed from riscv/insns/mov_us.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vmvv.h (renamed from riscv/insns/mov_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsb.h (renamed from riscv/insns/sb_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsd.h (renamed from riscv/insns/sd_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsetvl.h (renamed from riscv/insns/setvl.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsh.h (renamed from riscv/insns/sh_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssegb.h (renamed from riscv/insns/shseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssegd.h (renamed from riscv/insns/shsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssegh.h (renamed from riscv/insns/swseg_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssegstb.h (renamed from riscv/insns/swsegst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssegstd.h | 0 | ||||
-rw-r--r-- | riscv/insns/vssegsth.h | 0 | ||||
-rw-r--r-- | riscv/insns/vssegstw.h | 0 | ||||
-rw-r--r-- | riscv/insns/vssegw.h | 0 | ||||
-rw-r--r-- | riscv/insns/vsstb.h (renamed from riscv/insns/sbst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsstd.h (renamed from riscv/insns/sdst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vssth.h (renamed from riscv/insns/shst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsstw.h (renamed from riscv/insns/swst_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vsw.h (renamed from riscv/insns/sw_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vtcfgivl.h | 0 | ||||
-rw-r--r-- | riscv/insns/vvcfgivl.h (renamed from riscv/insns/vcfgivl.h) | 0 |
76 files changed, 212 insertions, 202 deletions
diff --git a/riscv/execute.h b/riscv/execute.h index b258957..6ea79c8 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -113,359 +113,319 @@ switch((insn.bits >> 0x0) & 0x7f) } case 0xb: { - if((insn.bits & 0x1ffff) == 0x230b) + if((insn.bits & 0x1ffff) == 0x128b) { - #include "insns/lwuseg_v.h" + #include "insns/vlsthu.h" break; } - if((insn.bits & 0x3fffff) == 0x10b) + if((insn.bits & 0xfff) == 0xb0b) { - #include "insns/lw_v.h" + #include "insns/vlsegstwu.h" break; } if((insn.bits & 0x3fffff) == 0x30b) { - #include "insns/lwu_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x1810b) - { - #include "insns/fmov_su.h" + #include "insns/vlwu.h" break; } - if((insn.bits & 0x1ffff) == 0x290b) - { - #include "insns/swseg_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x280b) + if((insn.bits & 0x3fffff) == 0x8b) { - #include "insns/sbseg_v.h" + #include "insns/vlh.h" break; } - if((insn.bits & 0x3fffff) == 0x20b) + if((insn.bits & 0x1ffff) == 0x158b) { - #include "insns/lbu_v.h" + #include "insns/vflstd.h" break; } - if((insn.bits & 0x1ffff) == 0x100b) + if((insn.bits & 0x3fffff) == 0xb) { - #include "insns/lbst_v.h" + #include "insns/vlb.h" break; } - if((insn.bits & 0x1ffff) == 0x218b) + if((insn.bits & 0x3fffff) == 0x18b) { - #include "insns/ldseg_v.h" + #include "insns/vld.h" break; } - if((insn.bits & 0x1ffff) == 0x180b) + if((insn.bits & 0x1ffff) == 0x150b) { - #include "insns/sbst_v.h" + #include "insns/vflstw.h" break; } - if((insn.bits & 0x3fffff) == 0x58b) + if((insn.bits & 0x3fffff) == 0x10b) { - #include "insns/fld_v.h" + #include "insns/vlw.h" break; } - if((insn.bits & 0x1ffff) == 0x208b) + if((insn.bits & 0x1ffff) == 0x120b) { - #include "insns/lhseg_v.h" + #include "insns/vlstbu.h" break; } if((insn.bits & 0x1ffff) == 0x220b) { - #include "insns/lbuseg_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x108b) - { - #include "insns/lhst_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x128b) - { - #include "insns/lhust_v.h" + #include "insns/vlsegbu.h" break; } - if((insn.bits & 0x3fffff) == 0x1008b) + if((insn.bits & 0xfff) == 0xa8b) { - #include "insns/mov_sv.h" + #include "insns/vlsegsthu.h" break; } - if((insn.bits & 0x1ffff) == 0x1010b) + if((insn.bits & 0x1ffff) == 0x110b) { - #include "insns/mov_su.h" + #include "insns/vlstw.h" break; } - if((insn.bits & 0x3fffff) == 0x18b) + if((insn.bits & 0x1ffff) == 0x108b) { - #include "insns/ld_v.h" + #include "insns/vlsth.h" break; } - if((insn.bits & 0x1ffff) == 0x1d0b) + if((insn.bits & 0x1ffff) == 0x100b) { - #include "insns/fswst_v.h" + #include "insns/vlstb.h" break; } - if((insn.bits & 0x3fffff) == 0xd8b) + if((insn.bits & 0x1ffff) == 0x118b) { - #include "insns/fsd_v.h" + #include "insns/vlstd.h" break; } - if((insn.bits & 0x3fffff) == 0x1808b) + if((insn.bits & 0xfff) == 0xa0b) { - #include "insns/fmov_sv.h" + #include "insns/vlsegstbu.h" break; } - if((insn.bits & 0x1ffff) == 0x2d8b) + if((insn.bits & 0x3fffff) == 0x28b) { - #include "insns/fsdseg_v.h" + #include "insns/vlhu.h" break; } - if((insn.bits & 0x1ffff) == 0x190b) + if((insn.bits & 0xfff) == 0x90b) { - #include "insns/swst_v.h" + #include "insns/vlsegstw.h" break; } - if((insn.bits & 0x1ffff) == 0x1d8b) + if((insn.bits & 0x1ffff) == 0x130b) { - #include "insns/fsdst_v.h" + #include "insns/vlstwu.h" break; } - if((insn.bits & 0x3fffff) == 0xb) + if((insn.bits & 0xfff) == 0x80b) { - #include "insns/lb_v.h" + #include "insns/vlsegstb.h" break; } - if((insn.bits & 0x1ffff) == 0x118b) + if((insn.bits & 0xfff) == 0x98b) { - #include "insns/ldst_v.h" + #include "insns/vlsegstd.h" break; } if((insn.bits & 0x1ffff) == 0x258b) { - #include "insns/fldseg_v.h" + #include "insns/vflsegd.h" break; } - if((insn.bits & 0x3fffff) == 0x8b) - { - #include "insns/lh_v.h" - break; - } - if((insn.bits & 0x3fffff) == 0x28b) + if((insn.bits & 0x1ffff) == 0x250b) { - #include "insns/lhu_v.h" + #include "insns/vflsegw.h" break; } - if((insn.bits & 0x1ffff) == 0x1018b) + if((insn.bits & 0xfff) == 0x88b) { - #include "insns/mov_us.h" + #include "insns/vlsegsth.h" break; } - if((insn.bits & 0x3fffff) == 0xd0b) + if((insn.bits & 0xfff) == 0xd0b) { - #include "insns/fsw_v.h" + #include "insns/vflsegstw.h" break; } - if((insn.bits & 0x1ffff) == 0x158b) + if((insn.bits & 0xfff) == 0xd8b) { - #include "insns/fldst_v.h" + #include "insns/vflsegstd.h" break; } - if((insn.bits & 0x1ffff) == 0x250b) + if((insn.bits & 0x3fffff) == 0x58b) { - #include "insns/flwseg_v.h" + #include "insns/vfld.h" break; } - if((insn.bits & 0x1ffff) == 0x200b) + if((insn.bits & 0x1ffff) == 0x230b) { - #include "insns/lbseg_v.h" + #include "insns/vlsegwu.h" break; } if((insn.bits & 0x3fffff) == 0x50b) { - #include "insns/flw_v.h" - break; - } - if((insn.bits & 0x3fffff) == 0x90b) - { - #include "insns/sw_v.h" + #include "insns/vflw.h" break; } - if((insn.bits & 0x1ffff) == 0x298b) - { - #include "insns/sdseg_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x130b) + if((insn.bits & 0x1ffff) == 0x200b) { - #include "insns/lwust_v.h" + #include "insns/vlsegb.h" break; } - if((insn.bits & 0x1ffff) == 0x150b) + if((insn.bits & 0x1ffff) == 0x218b) { - #include "insns/flwst_v.h" + #include "insns/vlsegd.h" break; } - if((insn.bits & 0x3fffff) == 0x88b) + if((insn.bits & 0x1ffff) == 0x208b) { - #include "insns/sh_v.h" + #include "insns/vlsegh.h" break; } if((insn.bits & 0x1ffff) == 0x210b) { - #include "insns/lwseg_v.h" - break; - } - if((insn.bits & 0x1ffff) == 0x2d0b) - { - #include "insns/fswseg_v.h" + #include "insns/vlsegw.h" break; } - if((insn.bits & 0x1ffff) == 0x288b) + if((insn.bits & 0x3fffff) == 0x20b) { - #include "insns/shseg_v.h" + #include "insns/vlbu.h" break; } - if((insn.bits & 0x1ffff) == 0x1818b) + if((insn.bits & 0x1ffff) == 0x228b) { - #include "insns/fmov_us.h" + #include "insns/vlseghu.h" break; } - if((insn.bits & 0x1ffff) == 0x228b) + throw trap_illegal_instruction; + break; + } + case 0xc: + { + #include "insns/c_sd.h" + break; + } + case 0xd: + { + #include "insns/c_sw.h" + break; + } + case 0xf: + { + if((insn.bits & 0x1ffff) == 0x150f) { - #include "insns/lhuseg_v.h" + #include "insns/vfsstw.h" break; } - if((insn.bits & 0x1ffff) == 0x120b) + if((insn.bits & 0xfff) == 0x90f) { - #include "insns/lbust_v.h" + #include "insns/vssegstw.h" break; } - if((insn.bits & 0x3fffff) == 0x98b) + if((insn.bits & 0xfff) == 0x98f) { - #include "insns/sd_v.h" + #include "insns/vssegstd.h" break; } - if((insn.bits & 0x3fffff) == 0x1000b) + if((insn.bits & 0xfff) == 0x80f) { - #include "insns/mov_vv.h" + #include "insns/vssegstb.h" break; } - if((insn.bits & 0x1ffff) == 0x110b) + if((insn.bits & 0xfff) == 0x88f) { - #include "insns/lwst_v.h" + #include "insns/vssegsth.h" break; } - if((insn.bits & 0x1ffff) == 0x198b) + if((insn.bits & 0x3fffff) == 0x10f) { - #include "insns/sdst_v.h" + #include "insns/vsw.h" break; } - if((insn.bits & 0x3fffff) == 0x1800b) + if((insn.bits & 0xfff) == 0xd8f) { - #include "insns/fmov_vv.h" + #include "insns/vfssegstd.h" break; } - if((insn.bits & 0x1ffff) == 0x188b) + if((insn.bits & 0x3fffff) == 0xf) { - #include "insns/shst_v.h" + #include "insns/vsb.h" break; } - if((insn.bits & 0x3fffff) == 0x80b) + if((insn.bits & 0x1ffff) == 0x110f) { - #include "insns/sb_v.h" + #include "insns/vsstw.h" break; } - throw trap_illegal_instruction; - break; - } - case 0xc: - { - #include "insns/c_sd.h" - break; - } - case 0xd: - { - #include "insns/c_sw.h" - break; - } - case 0xf: - { - if((insn.bits & 0xfff) == 0x20f) + if((insn.bits & 0x1ffff) == 0x108f) { - #include "insns/lbusegst_v.h" + #include "insns/vssth.h" break; } - if((insn.bits & 0xfff) == 0x18f) + if((insn.bits & 0x1ffff) == 0x100f) { - #include "insns/ldsegst_v.h" + #include "insns/vsstb.h" break; } - if((insn.bits & 0xfff) == 0x98f) + if((insn.bits & 0x1ffff) == 0x118f) { - #include "insns/sdsegst_v.h" + #include "insns/vsstd.h" break; } - if((insn.bits & 0xfff) == 0x30f) + if((insn.bits & 0x1ffff) == 0x218f) { - #include "insns/lwusegst_v.h" + #include "insns/vssegd.h" break; } - if((insn.bits & 0xfff) == 0x80f) + if((insn.bits & 0x1ffff) == 0x158f) { - #include "insns/sbsegst_v.h" + #include "insns/vfsstd.h" break; } - if((insn.bits & 0xfff) == 0x58f) + if((insn.bits & 0xfff) == 0xd0f) { - #include "insns/fldsegst_v.h" + #include "insns/vfssegstw.h" break; } - if((insn.bits & 0xfff) == 0x28f) + if((insn.bits & 0x1ffff) == 0x210f) { - #include "insns/lhusegst_v.h" + #include "insns/vssegw.h" break; } - if((insn.bits & 0xfff) == 0xf) + if((insn.bits & 0x3fffff) == 0x18f) { - #include "insns/lbsegst_v.h" + #include "insns/vsd.h" break; } - if((insn.bits & 0xfff) == 0xd8f) + if((insn.bits & 0x3fffff) == 0x8f) { - #include "insns/fsdsegst_v.h" + #include "insns/vsh.h" break; } - if((insn.bits & 0xfff) == 0xd0f) + if((insn.bits & 0x1ffff) == 0x208f) { - #include "insns/fswsegst_v.h" + #include "insns/vssegh.h" break; } - if((insn.bits & 0xfff) == 0x88f) + if((insn.bits & 0x3fffff) == 0x50f) { - #include "insns/shsegst_v.h" + #include "insns/vfsw.h" break; } - if((insn.bits & 0xfff) == 0x50f) + if((insn.bits & 0x3fffff) == 0x58f) { - #include "insns/flwsegst_v.h" + #include "insns/vfsd.h" break; } - if((insn.bits & 0xfff) == 0x10f) + if((insn.bits & 0x1ffff) == 0x250f) { - #include "insns/lwsegst_v.h" + #include "insns/vfssegw.h" break; } - if((insn.bits & 0xfff) == 0x90f) + if((insn.bits & 0x1ffff) == 0x200f) { - #include "insns/swsegst_v.h" + #include "insns/vssegb.h" break; } - if((insn.bits & 0xfff) == 0x8f) + if((insn.bits & 0x1ffff) == 0x258f) { - #include "insns/lhsegst_v.h" + #include "insns/vfssegd.h" break; } throw trap_illegal_instruction; @@ -583,14 +543,14 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/c_srai32.h" break; } - if((insn.bits & 0x1c1f) == 0xc19) + if((insn.bits & 0x1c1f) == 0x1819) { - #include "insns/c_srli32.h" + #include "insns/c_slliw.h" break; } - if((insn.bits & 0x1c1f) == 0x1819) + if((insn.bits & 0x1c1f) == 0xc19) { - #include "insns/c_slliw.h" + #include "insns/c_srli32.h" break; } if((insn.bits & 0x1c1f) == 0x1019) @@ -1063,14 +1023,14 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/c_srai32.h" break; } - if((insn.bits & 0x1c1f) == 0xc19) + if((insn.bits & 0x1c1f) == 0x1819) { - #include "insns/c_srli32.h" + #include "insns/c_slliw.h" break; } - if((insn.bits & 0x1c1f) == 0x1819) + if((insn.bits & 0x1c1f) == 0xc19) { - #include "insns/c_slliw.h" + #include "insns/c_srli32.h" break; } if((insn.bits & 0x1c1f) == 0x1019) @@ -1493,11 +1453,6 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fsgnjn_d.h" break; } - if((insn.bits & 0x3ff1ff) == 0xa053) - { - #include "insns/fcvt_w_s.h" - break; - } if((insn.bits & 0x3ff1ff) == 0xd0d3) { #include "insns/fcvt_d_lu.h" @@ -1563,6 +1518,11 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fsub_d.h" break; } + if((insn.bits & 0x3ff1ff) == 0xa053) + { + #include "insns/fcvt_w_s.h" + break; + } if((insn.bits & 0x3ff1ff) == 0x4053) { #include "insns/fsqrt_s.h" @@ -1628,14 +1588,14 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/c_srai32.h" break; } - if((insn.bits & 0x1c1f) == 0xc19) + if((insn.bits & 0x1c1f) == 0x1819) { - #include "insns/c_srli32.h" + #include "insns/c_slliw.h" break; } - if((insn.bits & 0x1c1f) == 0x1819) + if((insn.bits & 0x1c1f) == 0xc19) { - #include "insns/c_slliw.h" + #include "insns/c_srli32.h" break; } if((insn.bits & 0x1c1f) == 0x1019) @@ -1858,19 +1818,64 @@ switch((insn.bits >> 0x0) & 0x7f) } case 0x73: { - if((insn.bits & 0x3ff) == 0x73) + if((insn.bits & 0x3ff) == 0xf3) + { + #include "insns/vvcfgivl.h" + break; + } + if((insn.bits & 0x3fffff) == 0x2f3) { - #include "insns/vcfgivl.h" + #include "insns/vsetvl.h" break; } - if((insn.bits & 0xf80003ff) == 0x173) + if((insn.bits & 0x1ffff) == 0x1173) + { + #include "insns/vfmst.h" + break; + } + if((insn.bits & 0x1ffff) == 0x1973) + { + #include "insns/vfmts.h" + break; + } + if((insn.bits & 0x3fffff) == 0x973) + { + #include "insns/vfmsv.h" + break; + } + if((insn.bits & 0x1ffff) == 0x1873) + { + #include "insns/vmts.h" + break; + } + if((insn.bits & 0x3fffff) == 0x73) + { + #include "insns/vmvv.h" + break; + } + if((insn.bits & 0x3ff) == 0x1f3) + { + #include "insns/vtcfgivl.h" + break; + } + if((insn.bits & 0xf80003ff) == 0x3f3) { #include "insns/vf.h" break; } - if((insn.bits & 0x3fffff) == 0xf3) + if((insn.bits & 0x3fffff) == 0x173) + { + #include "insns/vfmvv.h" + break; + } + if((insn.bits & 0x3fffff) == 0x873) + { + #include "insns/vmsv.h" + break; + } + if((insn.bits & 0x1ffff) == 0x1073) { - #include "insns/setvl.h" + #include "insns/vmst.h" break; } throw trap_illegal_instruction; @@ -1893,9 +1898,14 @@ switch((insn.bits >> 0x0) & 0x7f) } case 0x77: { - if((insn.bits & 0x7ffffff) == 0x277) + if((insn.bits & 0x1ffff) == 0x2f7) { - #include "insns/rdcycle.h" + #include "insns/movn.h" + break; + } + if((insn.bits & 0x1ffff) == 0x277) + { + #include "insns/movz.h" break; } if((insn.bits & 0xffffffff) == 0x177) @@ -1913,14 +1923,14 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/utidx.h" break; } - if((insn.bits & 0x7ffffff) == 0xa77) + if((insn.bits & 0x1ffff) == 0x3f7) { - #include "insns/rdinstret.h" + #include "insns/fmovn.h" break; } - if((insn.bits & 0x7ffffff) == 0x677) + if((insn.bits & 0x1ffff) == 0x377) { - #include "insns/rdtime.h" + #include "insns/fmovz.h" break; } if((insn.bits & 0xffffffff) == 0x77) @@ -1953,14 +1963,14 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/c_srai32.h" break; } - if((insn.bits & 0x1c1f) == 0xc19) + if((insn.bits & 0x1c1f) == 0x1819) { - #include "insns/c_srli32.h" + #include "insns/c_slliw.h" break; } - if((insn.bits & 0x1c1f) == 0x1819) + if((insn.bits & 0x1c1f) == 0xc19) { - #include "insns/c_slliw.h" + #include "insns/c_srli32.h" break; } if((insn.bits & 0x1c1f) == 0x1019) diff --git a/riscv/insns/fldseg_v.h b/riscv/insns/fmovn.h index e69de29..e69de29 100644 --- a/riscv/insns/fldseg_v.h +++ b/riscv/insns/fmovn.h diff --git a/riscv/insns/fldsegst_v.h b/riscv/insns/fmovz.h index e69de29..e69de29 100644 --- a/riscv/insns/fldsegst_v.h +++ b/riscv/insns/fmovz.h diff --git a/riscv/insns/flwseg_v.h b/riscv/insns/movn.h index e69de29..e69de29 100644 --- a/riscv/insns/flwseg_v.h +++ b/riscv/insns/movn.h diff --git a/riscv/insns/flwsegst_v.h b/riscv/insns/movz.h index e69de29..e69de29 100644 --- a/riscv/insns/flwsegst_v.h +++ b/riscv/insns/movz.h diff --git a/riscv/insns/fld_v.h b/riscv/insns/vfld.h index 9b40470..9b40470 100644 --- a/riscv/insns/fld_v.h +++ b/riscv/insns/vfld.h diff --git a/riscv/insns/fsdseg_v.h b/riscv/insns/vflsegd.h index e69de29..e69de29 100644 --- a/riscv/insns/fsdseg_v.h +++ b/riscv/insns/vflsegd.h diff --git a/riscv/insns/fsdsegst_v.h b/riscv/insns/vflsegstd.h index e69de29..e69de29 100644 --- a/riscv/insns/fsdsegst_v.h +++ b/riscv/insns/vflsegstd.h diff --git a/riscv/insns/fswseg_v.h b/riscv/insns/vflsegstw.h index e69de29..e69de29 100644 --- a/riscv/insns/fswseg_v.h +++ b/riscv/insns/vflsegstw.h diff --git a/riscv/insns/fswsegst_v.h b/riscv/insns/vflsegw.h index e69de29..e69de29 100644 --- a/riscv/insns/fswsegst_v.h +++ b/riscv/insns/vflsegw.h diff --git a/riscv/insns/fldst_v.h b/riscv/insns/vflstd.h index fa9b32d..fa9b32d 100644 --- a/riscv/insns/fldst_v.h +++ b/riscv/insns/vflstd.h diff --git a/riscv/insns/flwst_v.h b/riscv/insns/vflstw.h index 716c818..716c818 100644 --- a/riscv/insns/flwst_v.h +++ b/riscv/insns/vflstw.h diff --git a/riscv/insns/flw_v.h b/riscv/insns/vflw.h index 75fdd04..75fdd04 100644 --- a/riscv/insns/flw_v.h +++ b/riscv/insns/vflw.h diff --git a/riscv/insns/fmov_su.h b/riscv/insns/vfmst.h index 20fa123..20fa123 100644 --- a/riscv/insns/fmov_su.h +++ b/riscv/insns/vfmst.h diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/vfmsv.h index a9aa876..a9aa876 100644 --- a/riscv/insns/fmov_sv.h +++ b/riscv/insns/vfmsv.h diff --git a/riscv/insns/fmov_us.h b/riscv/insns/vfmts.h index 6f56b25..6f56b25 100644 --- a/riscv/insns/fmov_us.h +++ b/riscv/insns/vfmts.h diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/vfmvv.h index 279da21..279da21 100644 --- a/riscv/insns/fmov_vv.h +++ b/riscv/insns/vfmvv.h diff --git a/riscv/insns/fsd_v.h b/riscv/insns/vfsd.h index f619fc8..f619fc8 100644 --- a/riscv/insns/fsd_v.h +++ b/riscv/insns/vfsd.h diff --git a/riscv/insns/lbseg_v.h b/riscv/insns/vfssegd.h index e69de29..e69de29 100644 --- a/riscv/insns/lbseg_v.h +++ b/riscv/insns/vfssegd.h diff --git a/riscv/insns/lbsegst_v.h b/riscv/insns/vfssegstd.h index e69de29..e69de29 100644 --- a/riscv/insns/lbsegst_v.h +++ b/riscv/insns/vfssegstd.h diff --git a/riscv/insns/lbuseg_v.h b/riscv/insns/vfssegstw.h index e69de29..e69de29 100644 --- a/riscv/insns/lbuseg_v.h +++ b/riscv/insns/vfssegstw.h diff --git a/riscv/insns/lbusegst_v.h b/riscv/insns/vfssegw.h index e69de29..e69de29 100644 --- a/riscv/insns/lbusegst_v.h +++ b/riscv/insns/vfssegw.h diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/vfsstd.h index b3bb260..b3bb260 100644 --- a/riscv/insns/fsdst_v.h +++ b/riscv/insns/vfsstd.h diff --git a/riscv/insns/fswst_v.h b/riscv/insns/vfsstw.h index 9cef9b0..9cef9b0 100644 --- a/riscv/insns/fswst_v.h +++ b/riscv/insns/vfsstw.h diff --git a/riscv/insns/fsw_v.h b/riscv/insns/vfsw.h index 3fe3d3f..3fe3d3f 100644 --- a/riscv/insns/fsw_v.h +++ b/riscv/insns/vfsw.h diff --git a/riscv/insns/lb_v.h b/riscv/insns/vlb.h index 618380a..618380a 100644 --- a/riscv/insns/lb_v.h +++ b/riscv/insns/vlb.h diff --git a/riscv/insns/lbu_v.h b/riscv/insns/vlbu.h index f92c8b5..f92c8b5 100644 --- a/riscv/insns/lbu_v.h +++ b/riscv/insns/vlbu.h diff --git a/riscv/insns/ld_v.h b/riscv/insns/vld.h index fb7a3c5..fb7a3c5 100644 --- a/riscv/insns/ld_v.h +++ b/riscv/insns/vld.h diff --git a/riscv/insns/lh_v.h b/riscv/insns/vlh.h index 269c2a8..269c2a8 100644 --- a/riscv/insns/lh_v.h +++ b/riscv/insns/vlh.h diff --git a/riscv/insns/lhu_v.h b/riscv/insns/vlhu.h index 7a2019d..7a2019d 100644 --- a/riscv/insns/lhu_v.h +++ b/riscv/insns/vlhu.h diff --git a/riscv/insns/ldseg_v.h b/riscv/insns/vlsegb.h index e69de29..e69de29 100644 --- a/riscv/insns/ldseg_v.h +++ b/riscv/insns/vlsegb.h diff --git a/riscv/insns/ldsegst_v.h b/riscv/insns/vlsegbu.h index e69de29..e69de29 100644 --- a/riscv/insns/ldsegst_v.h +++ b/riscv/insns/vlsegbu.h diff --git a/riscv/insns/lhseg_v.h b/riscv/insns/vlsegd.h index e69de29..e69de29 100644 --- a/riscv/insns/lhseg_v.h +++ b/riscv/insns/vlsegd.h diff --git a/riscv/insns/lhsegst_v.h b/riscv/insns/vlsegh.h index e69de29..e69de29 100644 --- a/riscv/insns/lhsegst_v.h +++ b/riscv/insns/vlsegh.h diff --git a/riscv/insns/lhuseg_v.h b/riscv/insns/vlseghu.h index e69de29..e69de29 100644 --- a/riscv/insns/lhuseg_v.h +++ b/riscv/insns/vlseghu.h diff --git a/riscv/insns/lhusegst_v.h b/riscv/insns/vlsegstb.h index e69de29..e69de29 100644 --- a/riscv/insns/lhusegst_v.h +++ b/riscv/insns/vlsegstb.h diff --git a/riscv/insns/lwseg_v.h b/riscv/insns/vlsegstbu.h index e69de29..e69de29 100644 --- a/riscv/insns/lwseg_v.h +++ b/riscv/insns/vlsegstbu.h diff --git a/riscv/insns/lwsegst_v.h b/riscv/insns/vlsegstd.h index e69de29..e69de29 100644 --- a/riscv/insns/lwsegst_v.h +++ b/riscv/insns/vlsegstd.h diff --git a/riscv/insns/lwuseg_v.h b/riscv/insns/vlsegsth.h index e69de29..e69de29 100644 --- a/riscv/insns/lwuseg_v.h +++ b/riscv/insns/vlsegsth.h diff --git a/riscv/insns/lwusegst_v.h b/riscv/insns/vlsegsthu.h index e69de29..e69de29 100644 --- a/riscv/insns/lwusegst_v.h +++ b/riscv/insns/vlsegsthu.h diff --git a/riscv/insns/sbseg_v.h b/riscv/insns/vlsegstw.h index e69de29..e69de29 100644 --- a/riscv/insns/sbseg_v.h +++ b/riscv/insns/vlsegstw.h diff --git a/riscv/insns/sbsegst_v.h b/riscv/insns/vlsegstwu.h index e69de29..e69de29 100644 --- a/riscv/insns/sbsegst_v.h +++ b/riscv/insns/vlsegstwu.h diff --git a/riscv/insns/sdseg_v.h b/riscv/insns/vlsegw.h index e69de29..e69de29 100644 --- a/riscv/insns/sdseg_v.h +++ b/riscv/insns/vlsegw.h diff --git a/riscv/insns/sdsegst_v.h b/riscv/insns/vlsegwu.h index e69de29..e69de29 100644 --- a/riscv/insns/sdsegst_v.h +++ b/riscv/insns/vlsegwu.h diff --git a/riscv/insns/lbst_v.h b/riscv/insns/vlstb.h index 219d90e..219d90e 100644 --- a/riscv/insns/lbst_v.h +++ b/riscv/insns/vlstb.h diff --git a/riscv/insns/lbust_v.h b/riscv/insns/vlstbu.h index 09faa29..09faa29 100644 --- a/riscv/insns/lbust_v.h +++ b/riscv/insns/vlstbu.h diff --git a/riscv/insns/ldst_v.h b/riscv/insns/vlstd.h index 5e5de9c..5e5de9c 100644 --- a/riscv/insns/ldst_v.h +++ b/riscv/insns/vlstd.h diff --git a/riscv/insns/lhst_v.h b/riscv/insns/vlsth.h index af6b5b5..af6b5b5 100644 --- a/riscv/insns/lhst_v.h +++ b/riscv/insns/vlsth.h diff --git a/riscv/insns/lhust_v.h b/riscv/insns/vlsthu.h index 0fe8452..0fe8452 100644 --- a/riscv/insns/lhust_v.h +++ b/riscv/insns/vlsthu.h diff --git a/riscv/insns/lwst_v.h b/riscv/insns/vlstw.h index 5375dc0..5375dc0 100644 --- a/riscv/insns/lwst_v.h +++ b/riscv/insns/vlstw.h diff --git a/riscv/insns/lwust_v.h b/riscv/insns/vlstwu.h index 328e23f..328e23f 100644 --- a/riscv/insns/lwust_v.h +++ b/riscv/insns/vlstwu.h diff --git a/riscv/insns/lw_v.h b/riscv/insns/vlw.h index 6e35911..6e35911 100644 --- a/riscv/insns/lw_v.h +++ b/riscv/insns/vlw.h diff --git a/riscv/insns/lwu_v.h b/riscv/insns/vlwu.h index 4fa1489..4fa1489 100644 --- a/riscv/insns/lwu_v.h +++ b/riscv/insns/vlwu.h diff --git a/riscv/insns/mov_su.h b/riscv/insns/vmst.h index 7b7cae1..7b7cae1 100644 --- a/riscv/insns/mov_su.h +++ b/riscv/insns/vmst.h diff --git a/riscv/insns/mov_sv.h b/riscv/insns/vmsv.h index c6f4c2c..c6f4c2c 100644 --- a/riscv/insns/mov_sv.h +++ b/riscv/insns/vmsv.h diff --git a/riscv/insns/mov_us.h b/riscv/insns/vmts.h index a69e388..a69e388 100644 --- a/riscv/insns/mov_us.h +++ b/riscv/insns/vmts.h diff --git a/riscv/insns/mov_vv.h b/riscv/insns/vmvv.h index 91d63d4..91d63d4 100644 --- a/riscv/insns/mov_vv.h +++ b/riscv/insns/vmvv.h diff --git a/riscv/insns/sb_v.h b/riscv/insns/vsb.h index c3d5b9d..c3d5b9d 100644 --- a/riscv/insns/sb_v.h +++ b/riscv/insns/vsb.h diff --git a/riscv/insns/sd_v.h b/riscv/insns/vsd.h index 9c02069..9c02069 100644 --- a/riscv/insns/sd_v.h +++ b/riscv/insns/vsd.h diff --git a/riscv/insns/setvl.h b/riscv/insns/vsetvl.h index c2212ff..c2212ff 100644 --- a/riscv/insns/setvl.h +++ b/riscv/insns/vsetvl.h diff --git a/riscv/insns/sh_v.h b/riscv/insns/vsh.h index 623eda8..623eda8 100644 --- a/riscv/insns/sh_v.h +++ b/riscv/insns/vsh.h diff --git a/riscv/insns/shseg_v.h b/riscv/insns/vssegb.h index e69de29..e69de29 100644 --- a/riscv/insns/shseg_v.h +++ b/riscv/insns/vssegb.h diff --git a/riscv/insns/shsegst_v.h b/riscv/insns/vssegd.h index e69de29..e69de29 100644 --- a/riscv/insns/shsegst_v.h +++ b/riscv/insns/vssegd.h diff --git a/riscv/insns/swseg_v.h b/riscv/insns/vssegh.h index e69de29..e69de29 100644 --- a/riscv/insns/swseg_v.h +++ b/riscv/insns/vssegh.h diff --git a/riscv/insns/swsegst_v.h b/riscv/insns/vssegstb.h index e69de29..e69de29 100644 --- a/riscv/insns/swsegst_v.h +++ b/riscv/insns/vssegstb.h diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegstd.h diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegsth.h diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegstw.h diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegw.h diff --git a/riscv/insns/sbst_v.h b/riscv/insns/vsstb.h index b83cc50..b83cc50 100644 --- a/riscv/insns/sbst_v.h +++ b/riscv/insns/vsstb.h diff --git a/riscv/insns/sdst_v.h b/riscv/insns/vsstd.h index 26868d2..26868d2 100644 --- a/riscv/insns/sdst_v.h +++ b/riscv/insns/vsstd.h diff --git a/riscv/insns/shst_v.h b/riscv/insns/vssth.h index 3904331..3904331 100644 --- a/riscv/insns/shst_v.h +++ b/riscv/insns/vssth.h diff --git a/riscv/insns/swst_v.h b/riscv/insns/vsstw.h index 8f05953..8f05953 100644 --- a/riscv/insns/swst_v.h +++ b/riscv/insns/vsstw.h diff --git a/riscv/insns/sw_v.h b/riscv/insns/vsw.h index 662d4e3..662d4e3 100644 --- a/riscv/insns/sw_v.h +++ b/riscv/insns/vsw.h diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vtcfgivl.h diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vvcfgivl.h index 0ded9f8..0ded9f8 100644 --- a/riscv/insns/vcfgivl.h +++ b/riscv/insns/vvcfgivl.h |