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| author | Tim Newsome <tim@sifive.com> | 2022-04-22 10:48:00 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-22 10:48:00 -0700 |
| commit | 16413646bb44d8752c25f0f36745b6b74a2a1025 (patch) | |
| tree | 6bcdefb6e1c063e683d1987b777b3fca477768ff /riscv | |
| parent | d9131e3b1dc571a657f9615903d1b7220c7c7d7f (diff) | |
| download | spike-16413646bb44d8752c25f0f36745b6b74a2a1025.zip spike-16413646bb44d8752c25f0f36745b6b74a2a1025.tar.gz spike-16413646bb44d8752c25f0f36745b6b74a2a1025.tar.bz2 | |
Remove maskmax as a variable.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/triggers.cc | 4 | ||||
| -rw-r--r-- | riscv/triggers.h | 1 |
2 files changed, 2 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 1bcda2a..99e3597 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -4,7 +4,7 @@ namespace triggers { mcontrol_t::mcontrol_t() : - maskmax(0), select(false), timing(false), chain_bit(false), + select(false), timing(false), chain_bit(false), match(MATCH_EQUAL), m(false), h(false), s(false), u(false), execute_bit(false), store_bit(false), load_bit(false) { @@ -15,7 +15,7 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { auto xlen = proc->get_xlen(); v = set_field(v, MCONTROL_TYPE(xlen), 2); v = set_field(v, MCONTROL_DMODE(xlen), dmode); - v = set_field(v, MCONTROL_MASKMAX(xlen), maskmax); + v = set_field(v, MCONTROL_MASKMAX(xlen), 0); v = set_field(v, MCONTROL_SELECT, select); v = set_field(v, MCONTROL_TIMING, timing); v = set_field(v, MCONTROL_ACTION, action); diff --git a/riscv/triggers.h b/riscv/triggers.h index c21b638..1e74c91 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -96,7 +96,6 @@ private: bool simple_match(unsigned xlen, reg_t value) const; public: - uint8_t maskmax; bool select; bool timing; bool chain_bit; |