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authorAndrew Waterman <andrew@sifive.com>2020-09-24 17:34:24 -0700
committerAndrew Waterman <andrew@sifive.com>2020-09-24 17:34:24 -0700
commit14ad0d98e45c74e824592b9f2f8b65cf1c07ead1 (patch)
tree94d780b0ab94b6feb8550740b874aab12af04810 /riscv
parentc6a5585849f4d446706dfcc904b9a422bd2b3067 (diff)
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Correctly respect mstatus.TSR
It never has effect when V=1.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/insns/sret.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
index 4423506..315f4f0 100644
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@@ -1,7 +1,10 @@
require_extension('S');
-if (STATE.v && (STATE.prv == PRV_U || get_field(STATE.hstatus, HSTATUS_VTSR)))
- require_novirt();
-require_privilege(get_field(STATE.mstatus, MSTATUS_TSR) ? PRV_M : PRV_S);
+if (STATE.v) {
+ if (STATE.prv == PRV_U || get_field(STATE.hstatus, HSTATUS_VTSR))
+ require_novirt();
+} else {
+ require_privilege(get_field(STATE.mstatus, MSTATUS_TSR) ? PRV_M : PRV_S);
+}
reg_t next_pc = (STATE.v) ? p->get_state()->vsepc : p->get_state()->sepc;
set_pc_and_serialize(next_pc);
reg_t s = STATE.mstatus;