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| author | Tim Newsome <tim@sifive.com> | 2022-03-30 10:18:02 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
| commit | f381b841ceaf816745604b40b34c951f01d8d6d4 (patch) | |
| tree | b05a011f0e1a92c5341b0381a4228212ef712be0 /riscv/triggers.cc | |
| parent | 306b519e7a6e9eb8b3c5cf3942c0e8cd92d145ca (diff) | |
| download | spike-f381b841ceaf816745604b40b34c951f01d8d6d4.zip spike-f381b841ceaf816745604b40b34c951f01d8d6d4.tar.gz spike-f381b841ceaf816745604b40b34c951f01d8d6d4.tar.bz2 | |
Abstract away access to load/store/execute bits.
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index c368140..b80663d 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -5,8 +5,8 @@ namespace triggers { mcontrol_t::mcontrol_t() : type(2), maskmax(0), select(false), timing(false), chain_bit(false), - match(MATCH_EQUAL), m(false), h(false), s(false), u(false), execute(false), - store(false), load(false) + match(MATCH_EQUAL), m(false), h(false), s(false), u(false), + execute_bit(false), store_bit(false), load_bit(false) { } @@ -25,9 +25,9 @@ reg_t mcontrol_t::tdata1_read(const processor_t *proc) const noexcept { v = set_field(v, MCONTROL_H, h); v = set_field(v, MCONTROL_S, s); v = set_field(v, MCONTROL_U, u); - v = set_field(v, MCONTROL_EXECUTE, execute); - v = set_field(v, MCONTROL_STORE, store); - v = set_field(v, MCONTROL_LOAD, load); + v = set_field(v, MCONTROL_EXECUTE, execute_bit); + v = set_field(v, MCONTROL_STORE, store_bit); + v = set_field(v, MCONTROL_LOAD, load_bit); return v; } @@ -59,11 +59,11 @@ bool mcontrol_t::tdata1_write(processor_t *proc, const reg_t val) noexcept { h = get_field(val, MCONTROL_H); s = get_field(val, MCONTROL_S); u = get_field(val, MCONTROL_U); - execute = get_field(val, MCONTROL_EXECUTE); - store = get_field(val, MCONTROL_STORE); - load = get_field(val, MCONTROL_LOAD); + execute_bit = get_field(val, MCONTROL_EXECUTE); + store_bit = get_field(val, MCONTROL_STORE); + load_bit = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. - if (execute) + if (execute_bit) timing = 0; return true; } @@ -109,9 +109,9 @@ bool mcontrol_t::simple_match(unsigned xlen, reg_t value) const { match_result_t mcontrol_t::memory_access_match(processor_t *proc, operation_t operation, reg_t address, reg_t data) { state_t *state = proc->get_state(); - if ((operation == triggers::OPERATION_EXECUTE && !execute) || - (operation == triggers::OPERATION_STORE && !store) || - (operation == triggers::OPERATION_LOAD && !load) || + if ((operation == triggers::OPERATION_EXECUTE && !execute_bit) || + (operation == triggers::OPERATION_STORE && !store_bit) || + (operation == triggers::OPERATION_LOAD && !load_bit) || (state->prv == PRV_M && !m) || (state->prv == PRV_S && !s) || (state->prv == PRV_U && !u)) { |