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| author | Tim Newsome <tim@sifive.com> | 2022-03-24 11:39:39 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
| commit | cf0707f883d6f8a38e2b943f9a4a959226287d65 (patch) | |
| tree | 9020eae24073fd856bcd898f03af8a8118a1e4a4 /riscv/triggers.cc | |
| parent | 825b396c4dba96f9941fdc4a38301e890c8c9d12 (diff) | |
| download | spike-cf0707f883d6f8a38e2b943f9a4a959226287d65.zip spike-cf0707f883d6f8a38e2b943f9a4a959226287d65.tar.gz spike-cf0707f883d6f8a38e2b943f9a4a959226287d65.tar.bz2 | |
Make triggers::module_t::triggers private.
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 2cb4b13..3a782e1 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -65,7 +65,6 @@ bool mcontrol_t::tdata1_write(processor_t *proc, const reg_t val) noexcept { // Assume we're here because of csrw. if (execute) timing = 0; - proc->trigger_updated(); return true; } @@ -180,7 +179,9 @@ reg_t module_t::tdata1_read(const processor_t *proc, unsigned index) const noexc bool module_t::tdata1_write(processor_t *proc, unsigned index, const reg_t val) noexcept { - return triggers[index]->tdata1_write(proc, val); + bool result = triggers[index]->tdata1_write(proc, val); + proc->trigger_updated(&triggers); + return result; } reg_t module_t::tdata2_read(const processor_t *proc, unsigned index) const noexcept @@ -190,7 +191,9 @@ reg_t module_t::tdata2_read(const processor_t *proc, unsigned index) const noexc bool module_t::tdata2_write(processor_t *proc, unsigned index, const reg_t val) noexcept { - return triggers[index]->tdata2_write(proc, val); + bool result = triggers[index]->tdata2_write(proc, val); + proc->trigger_updated(&triggers); + return result; } |