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authorTim Newsome <tim@sifive.com>2022-03-24 11:22:33 -0700
committerTim Newsome <tim@sifive.com>2022-04-05 10:33:31 -0700
commit972943662c6e608e5d321c9128cdb9aaf903a4ae (patch)
tree8413a0780d5de48576d2a128878b7177eefe407d /riscv/triggers.cc
parentf3d14f936965fb48a140ab010a9e1b0b2908bf2d (diff)
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Don't access triggers vector directly from csrs.cc.
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r--riscv/triggers.cc20
1 files changed, 20 insertions, 0 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index 5b9d853..2cb4b13 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -173,5 +173,25 @@ match_result_t module_t::memory_access_match(action_t *action, operation_t opera
return MATCH_NONE;
}
+reg_t module_t::tdata1_read(const processor_t *proc, unsigned index) const noexcept
+{
+ return triggers[index]->tdata1_read(proc);
+}
+
+bool module_t::tdata1_write(processor_t *proc, unsigned index, const reg_t val) noexcept
+{
+ return triggers[index]->tdata1_write(proc, val);
+}
+
+reg_t module_t::tdata2_read(const processor_t *proc, unsigned index) const noexcept
+{
+ return triggers[index]->tdata2_read(proc);
+}
+
+bool module_t::tdata2_write(processor_t *proc, unsigned index, const reg_t val) noexcept
+{
+ return triggers[index]->tdata2_write(proc, val);
+}
+
};