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author | Tim Newsome <tim@sifive.com> | 2022-03-16 10:24:34 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:10:03 -0700 |
commit | 894f77677d2d6bb84cf57ddec68e87857df357a1 (patch) | |
tree | 0987ec3c7240f7570ad90d862bfd68241a63e2a0 /riscv/triggers.cc | |
parent | 21975f9ebc19c90798e0e559a015f352e45e3e50 (diff) | |
download | spike-894f77677d2d6bb84cf57ddec68e87857df357a1.zip spike-894f77677d2d6bb84cf57ddec68e87857df357a1.tar.gz spike-894f77677d2d6bb84cf57ddec68e87857df357a1.tar.bz2 |
Move tdata2 logic into trigger.
There isn't much logic, but different trigger types will have different
logic.
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r-- | riscv/triggers.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 5acca77..f6b6e7d 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -69,6 +69,18 @@ bool mcontrol_t::tdata1_write(processor_t *proc, const reg_t val) noexcept { return true; } +reg_t mcontrol_t::tdata2_read(const processor_t *proc) const noexcept { + return tdata2; +} + +bool mcontrol_t::tdata2_write(processor_t *proc, const reg_t val) noexcept { + if (dmode && !proc->get_state()->debug_mode) { + return false; + } + tdata2 = val; + return true; +} + module_t::module_t(unsigned count) : triggers(count) { for (unsigned i = 0; i < count; i++) { triggers[i] = new mcontrol_t(); |