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author | Tim Newsome <tim@sifive.com> | 2022-03-16 10:16:37 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:45 -0700 |
commit | 02b3b36901daa3e030af40c71ac2418fc80fd90e (patch) | |
tree | d4e74246cc2c120930aecfbe453a9441f7f909d7 /riscv/triggers.cc | |
parent | 9bd1f818aee132ca6434e0ecaf168821024b1adc (diff) | |
download | spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.zip spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.tar.gz spike-02b3b36901daa3e030af40c71ac2418fc80fd90e.tar.bz2 |
Move tdata1 write logic into triggers.
Diffstat (limited to 'riscv/triggers.cc')
-rw-r--r-- | riscv/triggers.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 7fb5e8c..527ae71 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -31,6 +31,31 @@ reg_t mcontrol_t::tdata1_read(const processor_t *proc) const noexcept { return v; } +bool mcontrol_t::tdata1_write(processor_t *proc, const reg_t val) noexcept { + if (dmode && !proc->get_state()->debug_mode) { + return false; + } + auto xlen = proc->get_xlen(); + dmode = get_field(val, MCONTROL_DMODE(xlen)); + select = get_field(val, MCONTROL_SELECT); + timing = get_field(val, MCONTROL_TIMING); + action = (triggers::action_t) get_field(val, MCONTROL_ACTION); + chain = get_field(val, MCONTROL_CHAIN); + match = (triggers::mcontrol_t::match_t) get_field(val, MCONTROL_MATCH); + m = get_field(val, MCONTROL_M); + h = get_field(val, MCONTROL_H); + s = get_field(val, MCONTROL_S); + u = get_field(val, MCONTROL_U); + execute = get_field(val, MCONTROL_EXECUTE); + store = get_field(val, MCONTROL_STORE); + load = get_field(val, MCONTROL_LOAD); + // Assume we're here because of csrw. + if (execute) + timing = 0; + proc->trigger_updated(); + return true; +} + module_t::module_t(unsigned count) : triggers(count) { for (unsigned i = 0; i < count; i++) { triggers[i] = new mcontrol_t(); |