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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:30:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:30:22 -0700 |
| commit | a80c695b1961ac40086494920f82e85a085ff358 (patch) | |
| tree | d7c938bdfb5aa80542e8a1f9a68421ec730ca703 /riscv/trap.h | |
| parent | 1fa2174178a5432443f114dfc059ba19c53b1fae (diff) | |
| download | spike-a80c695b1961ac40086494920f82e85a085ff358.zip spike-a80c695b1961ac40086494920f82e85a085ff358.tar.gz spike-a80c695b1961ac40086494920f82e85a085ff358.tar.bz2 | |
Separate page faults from physical memory access exceptions
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 7f35c5f..a289a68 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -45,16 +45,19 @@ class mem_trap_t : public trap_t }; DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) -DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) +DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) -DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault) -DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault) +DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) +DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) +DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) +DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) +DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) #endif |