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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 00:43:12 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 01:06:50 -0700 |
| commit | e7ac8f1820fb07c23bb0dcc2fad1ef9b8476f7ca (patch) | |
| tree | 1133427425ebdfa833aabc6d6aa25836409e7591 /riscv/trap.h | |
| parent | fa20cd3571490a901274b5b0d278d0a58af5aa3f (diff) | |
| download | spike-e7ac8f1820fb07c23bb0dcc2fad1ef9b8476f7ca.zip spike-e7ac8f1820fb07c23bb0dcc2fad1ef9b8476f7ca.tar.gz spike-e7ac8f1820fb07c23bb0dcc2fad1ef9b8476f7ca.tar.bz2 | |
trap: use reserved trap to issue unimplemented instruction
it is work around
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index b5b8a50..2d12395 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -58,6 +58,7 @@ DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) +DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, unimplemented_instruction) DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) #endif |