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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-09 16:12:07 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-09 16:39:53 -0700 |
| commit | e294c392c63b8be738a9493754d302da7e1bb76b (patch) | |
| tree | 1ce533e1667661817184d893432b068df2312f57 /riscv/trap.h | |
| parent | dfee432b27a5e03b91420d13e2dedae2ad0512ea (diff) | |
| download | spike-e294c392c63b8be738a9493754d302da7e1bb76b.zip spike-e294c392c63b8be738a9493754d302da7e1bb76b.tar.gz spike-e294c392c63b8be738a9493754d302da7e1bb76b.tar.bz2 | |
Upgrade to privileged architecture 1.7
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index aa4a4e1..b03bf67 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -45,11 +45,14 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault) DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault) -DECLARE_TRAP(CAUSE_ECALL, ecall) -DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) +DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) +DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall) +DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) #endif |