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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:43:48 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:43:48 -0700 |
| commit | 7b396b51a6c38bc3472ea9c995e8015b39f19c1f (patch) | |
| tree | 7d62fcfbc7b8abd24dcb9ae1117592ed3c96277f /riscv/trap.h | |
| parent | 8f4fb411b016846a539a1ff1cd645a555e3737be (diff) | |
| download | spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.zip spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.tar.gz spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.tar.bz2 | |
Set badaddr=0 on illegal instruction traps
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 20313e9..91e5223 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -46,7 +46,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) -DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) +DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) |