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| author | Anup Patel <anup.patel@wdc.com> | 2020-11-27 11:30:48 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-11-27 11:30:48 +0530 |
| commit | 457f628ad78efa305283ae6cc4dc1530fceffbe4 (patch) | |
| tree | 59a8895ea1f9f9eb555594ca898ead683980aee1 /riscv/trap.h | |
| parent | d6cf0d23635a53e5229e4ed317f1bcc58323b21a (diff) | |
| download | spike-457f628ad78efa305283ae6cc4dc1530fceffbe4.zip spike-457f628ad78efa305283ae6cc4dc1530fceffbe4.tar.gz spike-457f628ad78efa305283ae6cc4dc1530fceffbe4.tar.bz2 | |
Fix hstatus.GVA and mstatus.GVA updation
The hstatus.GVA and mstatus.GVA should be set only when guest virtual
address is written to stval or mtval CSRs at time of taking trap.
This patch update access, page fault, and guest page fault trap classes
so that we can pass gva flag correct from source of the trap.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 4431d8a..46114ec 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -68,16 +68,28 @@ class mem_trap_t : public trap_t #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \ public: \ + trap_##x(bool gva, reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, gva, tval, tval2, tinst) {} \ + const char* name() { return "trap_"#x; } \ +}; + +#define DECLARE_MEM_NOGVA_TRAP(n, x) class trap_##x : public mem_trap_t { \ + public: \ + trap_##x(reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, false, tval, tval2, tinst) {} \ + const char* name() { return "trap_"#x; } \ +}; + +#define DECLARE_MEM_GVA_TRAP(n, x) class trap_##x : public mem_trap_t { \ + public: \ trap_##x(reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, true, tval, tval2, tinst) {} \ const char* name() { return "trap_"#x; } \ }; -DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) +DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_INST_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_INST_TRAP(CAUSE_BREAKPOINT, breakpoint) -DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) -DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) +DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) +DECLARE_MEM_NOGVA_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) @@ -87,9 +99,9 @@ DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) -DECLARE_MEM_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault) -DECLARE_MEM_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault) +DECLARE_MEM_GVA_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault) +DECLARE_MEM_GVA_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault) DECLARE_INST_TRAP(CAUSE_VIRTUAL_INSTRUCTION, virtual_instruction) -DECLARE_MEM_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault) +DECLARE_MEM_GVA_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault) #endif |