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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 23:06:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 23:06:40 -0700 |
| commit | 384e03dde463d77f2e032ef6ab56e0b4b8be5e65 (patch) | |
| tree | d6075dd97cfd8e4590a36730bf00656330e9becb /riscv/trap.h | |
| parent | 11fad84fb19699c1333a72a615bc2f6557a6eed3 (diff) | |
| download | spike-384e03dde463d77f2e032ef6ab56e0b4b8be5e65.zip spike-384e03dde463d77f2e032ef6ab56e0b4b8be5e65.tar.gz spike-384e03dde463d77f2e032ef6ab56e0b4b8be5e65.tar.bz2 | |
Use hcall instead of mcall
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 7110073..8bc94f3 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -46,6 +46,7 @@ DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_TRAP(CAUSE_SCALL, scall) +DECLARE_TRAP(CAUSE_HCALL, hcall) DECLARE_TRAP(CAUSE_MCALL, mcall) DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) |