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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:34:26 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:34:26 -0700 |
| commit | 0f140bcde46a940f76d3e06857d3f572ab6966c4 (patch) | |
| tree | b6f8bb4215691c4a730d323d62ec82282f90e4ff /riscv/trap.h | |
| parent | 289e2118cb35c023c04085e731952edb70fc18a9 (diff) | |
| download | spike-0f140bcde46a940f76d3e06857d3f572ab6966c4.zip spike-0f140bcde46a940f76d3e06857d3f572ab6966c4.tar.gz spike-0f140bcde46a940f76d3e06857d3f572ab6966c4.tar.bz2 | |
add hwacha exception support
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index a7a823b..9a1a2f9 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -25,6 +25,7 @@ class mem_trap_t : public trap_t mem_trap_t(reg_t which, reg_t badvaddr) : trap_t(which), badvaddr(badvaddr) {} void side_effects(state_t* state); + reg_t get_badvaddr() { return badvaddr; } private: reg_t badvaddr; }; @@ -53,8 +54,5 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) -DECLARE_TRAP(12, vector_disabled) -DECLARE_TRAP(13, vector_bank) -DECLARE_TRAP(14, vector_illegal_instruction) #endif |