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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-20 07:11:31 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-20 08:01:59 -0700 |
| commit | 5720fb6d79c67d4a18de367aa546a1728202a407 (patch) | |
| tree | 432622bccb5634d7dd39bae2545d560ecb58dcf9 /riscv/simif.h | |
| parent | 1c558aa3a1d40d689230002bc2d7b7f299b66978 (diff) | |
| download | spike-5720fb6d79c67d4a18de367aa546a1728202a407.zip spike-5720fb6d79c67d4a18de367aa546a1728202a407.tar.gz spike-5720fb6d79c67d4a18de367aa546a1728202a407.tar.bz2 | |
add configurable LR/SC reservation set
Diffstat (limited to 'riscv/simif.h')
| -rw-r--r-- | riscv/simif.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/riscv/simif.h b/riscv/simif.h index 1d982b3..5834a87 100644 --- a/riscv/simif.h +++ b/riscv/simif.h @@ -4,6 +4,13 @@ #define _RISCV_SIMIF_H #include "decode.h" +#include <map> + +// LR/SC +struct reservation { + uint32_t id; + bool valid; +}; // this is the interface to the simulator used by the processors and memory class simif_t @@ -16,6 +23,10 @@ public: virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) = 0; + + // get the LR/SC's reservation set + virtual std::map<reg_t, reservation>& get_reservation_set() = 0; + virtual reg_t get_reservation_set_size() = 0; }; #endif |