diff options
| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-28 15:01:09 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-28 15:17:06 -0700 |
| commit | a9c5b05eca6a46a0c8722b26b741fc7f1de22405 (patch) | |
| tree | c5393d107dfa9fcee0b9d9b9cc14fca0900f1924 /riscv/sim.h | |
| parent | 27e29e69cc586a7d97e2ccae2447faa79b66f7b8 (diff) | |
| download | spike-a9c5b05eca6a46a0c8722b26b741fc7f1de22405.zip spike-a9c5b05eca6a46a0c8722b26b741fc7f1de22405.tar.gz spike-a9c5b05eca6a46a0c8722b26b741fc7f1de22405.tar.bz2 | |
Remove MTIME[CMP]; add RTC device
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 6745e75..89d3648 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -44,13 +44,14 @@ private: mmu_t* debug_mmu; // debug port into main memory std::vector<processor_t*> procs; std::unique_ptr<rom_device_t> config_string; + std::unique_ptr<rtc_t> rtc; + reg_t config_string_addr; bus_t bus; processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core - reg_t rtc; size_t current_step; size_t current_proc; bool debug; |