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| author | Tim Newsome <tim@sifive.com> | 2016-04-23 11:09:07 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 191671a2015136c429394fd3051e4a9c1ff45352 (patch) | |
| tree | 5ff49620581cec35ec650d6fe2b0d0eb07ccaf14 /riscv/sim.h | |
| parent | 78332ffbafeae5e9079bfc69ff136c5d24644a4c (diff) | |
| download | spike-191671a2015136c429394fd3051e4a9c1ff45352.zip spike-191671a2015136c429394fd3051e4a9c1ff45352.tar.gz spike-191671a2015136c429394fd3051e4a9c1ff45352.tar.bz2 | |
ROM -> RAM -> ROM, waiting for debug int.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index dad32ef..2e7b214 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -89,6 +89,11 @@ private: reg_t get_mem(const std::vector<std::string>& args); reg_t get_pc(const std::vector<std::string>& args); + // Return a pointer to Debug RAM in spike address space. + char *debug_ram() const { + return mem + memsz - DEBUG_SIZE + DEBUG_RAM_START - DEBUG_START; + } + friend class htif_isasim_t; friend class processor_t; friend class mmu_t; |