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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-11-12 17:51:46 -0800 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-11-12 17:52:56 -0800 |
commit | 0c3af3d73a28c0fc57eac535b2a28f45134b556b (patch) | |
tree | a9ad7bab1842bde77d6755d96b22a45a510e7a41 /riscv/sim.h | |
parent | a7bde15c2b79de12484748b462e511e0d1c2eca5 (diff) | |
download | spike-0c3af3d73a28c0fc57eac535b2a28f45134b556b.zip spike-0c3af3d73a28c0fc57eac535b2a28f45134b556b.tar.gz spike-0c3af3d73a28c0fc57eac535b2a28f45134b556b.tar.bz2 |
Generate device tree for target machine
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 636190e..6ef2c82 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -8,6 +8,7 @@ #include <memory> #include "processor.h" #include "mmu.h" +#include "devices.h" class htif_isasim_t; @@ -29,9 +30,6 @@ public: void set_procs_debug(bool value); htif_isasim_t* get_htif() { return htif.get(); } - // deliver an IPI to a specific processor - void send_ipi(reg_t who); - // returns the number of processors in this simulator size_t num_cores() { return procs.size(); } processor_t* get_core(size_t i) { return procs.at(i); } @@ -45,6 +43,8 @@ private: size_t memsz; // memory size in bytes mmu_t* debug_mmu; // debug port into main memory std::vector<processor_t*> procs; + std::unique_ptr<rom_device_t> devicetree; + bus_t bus; processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation @@ -60,6 +60,7 @@ private: // memory-mapped I/O routines bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); + void make_device_tree(); // presents a prompt for introspection into the simulation void interactive(); |