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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-03 18:51:37 -0800 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 15:03:38 -0700 |
| commit | fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363 (patch) | |
| tree | bf75fccf6028d0665ed614c9d6eaa5d512e3dac4 /riscv/sim.h | |
| parent | c71db7787b63fc1ab0c57672c9e469711748bda9 (diff) | |
| download | spike-fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363.zip spike-fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363.tar.gz spike-fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363.tar.bz2 | |
sim: define emulated CPU clock rate to be 1GHz
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 5d165c9..f655914 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -48,6 +48,7 @@ private: void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; |