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| author | Tim Newsome <tim@sifive.com> | 2019-04-04 14:34:33 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-14 01:50:01 -0700 |
| commit | bcba3fb4e419068e0196d8f758ccd8b37d7ef69a (patch) | |
| tree | cff1bee99c96b36c256c5e2cf3255c3cf396e2a5 /riscv/sim.h | |
| parent | 6dcf6d7503e0fd40e75210c76771690ff664f0d7 (diff) | |
| download | spike-bcba3fb4e419068e0196d8f758ccd8b37d7ef69a.zip spike-bcba3fb4e419068e0196d8f758ccd8b37d7ef69a.tar.gz spike-bcba3fb4e419068e0196d8f758ccd8b37d7ef69a.tar.bz2 | |
Add --debug-no-abstract-csr (#267)
This is used to make sure that OpenOCD can work on targets that don't
support abstract access to CSR registers. It replaces a simpler hack,
which caused #266.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 0ef9e46..90e3a5c 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -26,7 +26,7 @@ public: const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication, suseconds_t abstract_delay_usec, - bool support_hasel); + bool support_hasel, bool support_abstract_csr_access); ~sim_t(); // run the simulation to completion |