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authorAndy Wright <acwright@mit.edu>2018-05-31 13:53:12 -0400
committerAndrew Waterman <aswaterman@gmail.com>2018-05-31 10:53:12 -0700
commitabc7911a7c7929fa49b71cd37a75bd45e3f75d87 (patch)
treef4b65db4f03545a10815ec021a39b8aee64f8ffc /riscv/sim.h
parentbae2161ffb268389bca048b4dd358a0eec398703 (diff)
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Put simif_t declaration in its own file. (#209)
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r--riscv/sim.h14
1 files changed, 1 insertions, 13 deletions
diff --git a/riscv/sim.h b/riscv/sim.h
index 257de5b..97e9ede 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -6,6 +6,7 @@
#include "processor.h"
#include "devices.h"
#include "debug_module.h"
+#include "simif.h"
#include <fesvr/htif.h>
#include <fesvr/context.h>
#include <vector>
@@ -15,19 +16,6 @@
class mmu_t;
class remote_bitbang_t;
-// this is the interface to the simulator used by the processors and memory
-class simif_t
-{
-public:
- // should return NULL for MMIO addresses
- virtual char* addr_to_mem(reg_t addr) = 0;
- // used for MMIO addresses
- virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
- virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
- // Callback for processors to let the simulation know they were reset.
- virtual void proc_reset(unsigned id) = 0;
-};
-
// this class encapsulates the processors and memory in a RISC-V machine.
class sim_t : public htif_t, public simif_t
{