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| author | Tim Newsome <tim@sifive.com> | 2018-02-01 14:32:00 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-02-01 14:32:00 -0800 |
| commit | b2672e5d5271b346a71ec33ab42c88437b9b60d1 (patch) | |
| tree | 33b6e163c6e3d5c45bdbacb0fbda86f3a7b51abc /riscv/sim.h | |
| parent | d3d3681f3468c633bc93a727a35bc07348245440 (diff) | |
| download | spike-b2672e5d5271b346a71ec33ab42c88437b9b60d1.zip spike-b2672e5d5271b346a71ec33ab42c88437b9b60d1.tar.gz spike-b2672e5d5271b346a71ec33ab42c88437b9b60d1.tar.bz2 | |
Add --debug-sba option
This lets the user control whether the system bus access implements bus
mastering.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index e29cca4..47f3a45 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -22,7 +22,7 @@ public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, - unsigned progsize); + unsigned progsize, unsigned max_bus_master_bits); ~sim_t(); // run the simulation to completion |