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| author | Tim Newsome <tim@sifive.com> | 2018-03-16 14:52:09 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-03-16 14:52:35 -0700 |
| commit | 90bafe660b323250338fd564bb9ab4316576d59b (patch) | |
| tree | aa46de0e7ef641e1518253394073505d41ec0bac /riscv/sim.h | |
| parent | 403438d6096f4a6bf0ff924f60940acf51c529a5 (diff) | |
| download | spike-90bafe660b323250338fd564bb9ab4316576d59b.zip spike-90bafe660b323250338fd564bb9ab4316576d59b.tar.gz spike-90bafe660b323250338fd564bb9ab4316576d59b.tar.bz2 | |
Implement debug havereset bits
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 9a0a10b..257de5b 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -24,6 +24,8 @@ public: // used for MMIO addresses virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; + // Callback for processors to let the simulation know they were reset. + virtual void proc_reset(unsigned id) = 0; }; // this class encapsulates the processors and memory in a RISC-V machine. @@ -49,6 +51,9 @@ public: processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } + // Callback for processors to let the simulation know they were reset. + void proc_reset(unsigned id); + private: std::vector<std::pair<reg_t, mem_t*>> mems; mmu_t* debug_mmu; // debug port into main memory |