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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 16:57:10 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:17:23 -0800 |
| commit | 8ffefbc9a1f7730d14a2f694906bcc681cbca2e5 (patch) | |
| tree | 4ddbd6759b51f7bf2427db7d45bbdf9f9daa541e /riscv/sim.h | |
| parent | 24e587d43315dabaac2b7b8a631d459fc12f3f14 (diff) | |
| download | spike-8ffefbc9a1f7730d14a2f694906bcc681cbca2e5.zip spike-8ffefbc9a1f7730d14a2f694906bcc681cbca2e5.tar.gz spike-8ffefbc9a1f7730d14a2f694906bcc681cbca2e5.tar.bz2 | |
Add --priv option to control which privilege modes are available
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 0720ce4..3b7e25c 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -21,7 +21,8 @@ class remote_bitbang_t; class sim_t : public htif_t, public simif_t { public: - sim_t(const char* isa, const char* varch, size_t _nprocs, bool halted, + sim_t(const char* isa, const char* priv, const char* varch, size_t _nprocs, + bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices, const std::vector<std::string>& args, const std::vector<int> hartids, |