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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-23 16:54:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-23 16:54:36 -0700 |
| commit | 747a54b103160bcac7c9dcf721ce3b4703577d73 (patch) | |
| tree | 3ae17c87f4b9b0b0c26d82e1976f9965cee698c2 /riscv/sim.h | |
| parent | 60235e3816220eabc6f6e48d103889300d5547df (diff) | |
| download | spike-747a54b103160bcac7c9dcf721ce3b4703577d73.zip spike-747a54b103160bcac7c9dcf721ce3b4703577d73.tar.gz spike-747a54b103160bcac7c9dcf721ce3b4703577d73.tar.bz2 | |
Add --disable-dtb option to suppress writing the DTB to memory
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 97e9ede..b847bdb 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -32,6 +32,9 @@ public: void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); + void set_dtb_enabled(bool value) { + this->dtb_enabled = value; + } void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } @@ -62,6 +65,7 @@ private: bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs + bool dtb_enabled; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines |