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| author | Tim Newsome <tim@sifive.com> | 2019-04-04 14:34:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-04 14:34:33 -0700 |
| commit | 69a8b5d2cfc54c36c86b8733a1fbcdffe9811a94 (patch) | |
| tree | 7a5ec2a8021c4fd69f78b11ddd90d386eb9876bd /riscv/sim.h | |
| parent | 3e79495c38bf58df9c7b389205032b2eb3f45fb7 (diff) | |
| download | spike-69a8b5d2cfc54c36c86b8733a1fbcdffe9811a94.zip spike-69a8b5d2cfc54c36c86b8733a1fbcdffe9811a94.tar.gz spike-69a8b5d2cfc54c36c86b8733a1fbcdffe9811a94.tar.bz2 | |
Add --debug-no-abstract-csr (#267)
This is used to make sure that OpenOCD can work on targets that don't
support abstract access to CSR registers. It replaces a simpler hack,
which caused #266.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index ef3e780..d1c7a37 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -26,7 +26,7 @@ public: const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication, suseconds_t abstract_delay_usec, - bool support_hasel); + bool support_hasel, bool support_abstract_csr_access); ~sim_t(); // run the simulation to completion |