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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-02-20 15:16:53 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-06 12:07:03 -0600 |
commit | 4a97a05a6e806f7abcb6cd30685093aa5b9331a9 (patch) | |
tree | 8454d198cbb618ab3e120871f48b7c9c0503e06b /riscv/sim.h | |
parent | 58aa702359ec56f0b26a3f10a2617a58c9818451 (diff) | |
download | spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.zip spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.gz spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.bz2 |
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 47f3a45..638206e 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -15,8 +15,19 @@ class mmu_t; class remote_bitbang_t; +// this is the interface to the simulator used by the processors and memory +class simif_t +{ +public: + // should return NULL for MMIO addresses + virtual char* addr_to_mem(reg_t addr) = 0; + // used for MMIO addresses + virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; + virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; +}; + // this class encapsulates the processors and memory in a RISC-V machine. -class sim_t : public htif_t +class sim_t : public htif_t, public simif_t { public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, |