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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 02:54:46 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-14 07:42:30 -0700 |
| commit | 48fe0c484d50073bd5d12bdb7fef5b7ea257e006 (patch) | |
| tree | 3ebf533ff93788a3d2cf71308df568df117c53b1 /riscv/sim.h | |
| parent | 9de0cdda3f089bf1a73d39eb1abb1dafe8cdbbab (diff) | |
| download | spike-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.zip spike-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.tar.gz spike-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.tar.bz2 | |
rvv: add varch option parser and initialize vector unit
the default vector parameters are defined in configuration time but can
be changed throught command-line option
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 6b9fad5..3345da2 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -21,8 +21,8 @@ class remote_bitbang_t; class sim_t : public htif_t, public simif_t { public: - sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, - std::vector<std::pair<reg_t, mem_t*>> mems, + sim_t(const char* isa, const char* varch, size_t _nprocs, bool halted, + reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, const debug_module_config_t &dm_config); ~sim_t(); |