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| author | Tim Newsome <tim@sifive.com> | 2019-04-02 11:05:19 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-02 11:05:19 -0700 |
| commit | 3e79495c38bf58df9c7b389205032b2eb3f45fb7 (patch) | |
| tree | 4f14f114747d367e7d34e8edadd2f3597cae07a5 /riscv/sim.h | |
| parent | 994c07cb23dfd9f85d5e6d92aeeaece58bbb4183 (diff) | |
| download | spike-3e79495c38bf58df9c7b389205032b2eb3f45fb7.zip spike-3e79495c38bf58df9c7b389205032b2eb3f45fb7.tar.gz spike-3e79495c38bf58df9c7b389205032b2eb3f45fb7.tar.bz2 | |
Implement debug hasel support (#287)
* Implement hasel/hawindow support.
This should allow simultaneous resume and halt to work.
* Fix anyrunning/anyhalted bits.
* Add --without-hasel argument for testing.
* Make halt/resume times more equal.
Switching threads after every instruction executed in debug mode leads
to a lot of extra instructions being executed on the "other" thread when
both are really supposed to halt/resume near-simultaneously. Fixed that
by adding wfi to debug_rom.S, and implementing it to switch to the other
hart as well as check for JTAG input.
When resuming, write the hart ID to the debug ROM so that the DM knows
which hart actually resumed. (Before simultaneous resume it just assumed
the current one.)
Also got rid of resume symbol in debug_rom.S since it had no purpose.
* Preserve Debug ROM entry points.
* Make sure minstret is correct when wfi happens.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 1bb28cb..ef3e780 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -25,7 +25,8 @@ public: std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, - bool require_authentication, suseconds_t abstract_delay_usec); + bool require_authentication, suseconds_t abstract_delay_usec, + bool support_hasel); ~sim_t(); // run the simulation to completion |