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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/sim.cc | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | spike-990c6c48098e83584edf5282d119187abae04a4d.zip spike-990c6c48098e83584edf5282d119187abae04a4d.tar.gz spike-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index b09e720..4b4eed4 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -42,6 +42,8 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n", (unsigned long)memsz, (unsigned long)memsz0); + bus.add_device(DEBUG_START, &debug_module); + debug_mmu = new mmu_t(this, NULL); for (size_t i = 0; i < procs.size(); i++) { @@ -52,8 +54,6 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, rtc.reset(new rtc_t(procs)); make_config_string(); - - bus.add_device(DEBUG_START, &debug_module); } sim_t::~sim_t() @@ -149,11 +149,6 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) return bus.store(addr, len, bytes); } -char* sim_t::mmio_page(reg_t addr) -{ - return bus.page(addr); -} - void sim_t::make_config_string() { reg_t rtc_addr = EXT_IO_BASE; |