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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
| commit | 75f2a05df9cdff6f3faba748065b3184b9f01b01 (patch) | |
| tree | 634ef6316fc2aad26ff9100f38c5367ebe30f31b /riscv/sim.cc | |
| parent | 4859971a8879728378b0867e899b082e67737728 (diff) | |
| download | spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.zip spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.gz spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.bz2 | |
Set default entry point from ELF
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 59c4f0e..ebf94b6 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -45,8 +45,6 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, clint.reset(new clint_t(procs)); bus.add_device(CLINT_BASE, clint.get()); - - make_dtb(); } sim_t::~sim_t() @@ -230,6 +228,7 @@ void sim_t::make_dtb() { const int reset_vec_size = 8; + start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc; reg_t pc_delta = start_pc - DEFAULT_RSTVEC; reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU); reg_t pc_delta_lo = pc_delta - pc_delta_hi; @@ -325,6 +324,11 @@ char* sim_t::addr_to_mem(reg_t addr) { // htif +void sim_t::reset() +{ + make_dtb(); +} + void sim_t::idle() { target.switch_to(); |