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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-02-20 15:16:53 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-06 12:07:03 -0600 |
| commit | 4a97a05a6e806f7abcb6cd30685093aa5b9331a9 (patch) | |
| tree | 8454d198cbb618ab3e120871f48b7c9c0503e06b /riscv/sim.cc | |
| parent | 58aa702359ec56f0b26a3f10a2617a58c9818451 (diff) | |
| download | spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.zip spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.gz spike-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.bz2 | |
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 009bb98..10c1898 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -247,7 +247,7 @@ void sim_t::make_dtb() 0x297, // auipc t0,0x0 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb 0xf1402573, // csrr a0, mhartid - get_core(0)->xlen == 32 ? + get_core(0)->get_xlen() == 32 ? 0x0182a283u : // lw t0,24(t0) 0x0182b283u, // ld t0,24(t0) 0x28067, // jr t0 @@ -277,8 +277,8 @@ void sim_t::make_dtb() " reg = <" << i << ">;\n" " status = \"okay\";\n" " compatible = \"riscv\";\n" - " riscv,isa = \"" << procs[i]->isa_string << "\";\n" - " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" + " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n" + " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << CPU_HZ << ">;\n" " CPU" << i << "_intc: interrupt-controller {\n" " #interrupt-cells = <1>;\n" |