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| author | Elmar Melcher <elmar@dsc.ufcg.edu.br> | 2021-07-02 11:17:23 -0300 |
|---|---|---|
| committer | emelcher <elmar@dsc.ufcg.edu.br> | 2021-08-03 10:19:27 -0300 |
| commit | a5243f4520f3e9687974328f702a22c15e199596 (patch) | |
| tree | d950f99e9f2a9a431a423bddfa181f9b69a654bb /riscv/sim.cc | |
| parent | e30c9c90efa415a493ba2984a777bf53d1b8cbca (diff) | |
| download | spike-a5243f4520f3e9687974328f702a22c15e199596.zip spike-a5243f4520f3e9687974328f702a22c15e199596.tar.gz spike-a5243f4520f3e9687974328f702a22c15e199596.tar.bz2 | |
declare socket properties in processor_t
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 7b1e669..3c37c44 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -85,7 +85,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, for (size_t i = 0; i < nprocs; i++) { int hart_id = hartids.empty() ? i : hartids[i]; procs[i] = new processor_t(isa, priv, varch, this, hart_id, halted, - log_file.get()); + log_file.get(), &sout); } make_dtb(); |