aboutsummaryrefslogtreecommitdiff
path: root/riscv/sim.cc
diff options
context:
space:
mode:
authorMarcus Comstedt <marcus@mc.pp.se>2020-10-17 13:40:01 +0200
committerMarcus Comstedt <marcus@mc.pp.se>2020-11-07 15:34:19 +0100
commit8e3bcb2eef7f195a9cd61f5b79c1e67a0c3c28ff (patch)
tree191a89f0adab760eddfd0cf4a3e6ee11fbfd1b0f /riscv/sim.cc
parentec2fd09fdbb7b7b490cacdc3818ca237f9f28593 (diff)
downloadspike-8e3bcb2eef7f195a9cd61f5b79c1e67a0c3c28ff.zip
spike-8e3bcb2eef7f195a9cd61f5b79c1e67a0c3c28ff.tar.gz
spike-8e3bcb2eef7f195a9cd61f5b79c1e67a0c3c28ff.tar.bz2
Tag target endian values to help guide conversion code
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r--riscv/sim.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc
index ef405c3..6faa1ac 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -336,7 +336,7 @@ void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
{
assert(len == 8);
- uint64_t data;
+ target_endian<uint64_t> data;
memcpy(&data, src, sizeof data);
debug_mmu->store_uint64(taddr, debug_mmu->from_target(data));
}