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authorTim Newsome <tim@sifive.com>2017-06-14 12:42:00 -0700
committerAndrew Waterman <aswaterman@gmail.com>2017-06-14 12:54:43 -0700
commit1e2518d415ae8e9c8247d823fcb435ddbd0a0854 (patch)
treef305034104af560dbfe2183fad6c95d32798dc1e /riscv/sim.cc
parentf65e7e585f8ba596a74cb509502e6e2f7b3a8f43 (diff)
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Support 64-bit start PCs in reset vector.
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r--riscv/sim.cc22
1 files changed, 10 insertions, 12 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 42d60a1..647cc46 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -229,20 +229,18 @@ void sim_t::make_dtb()
const int reset_vec_size = 8;
start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
- reg_t pc_delta = start_pc - DEFAULT_RSTVEC;
- reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU);
- reg_t pc_delta_lo = pc_delta - pc_delta_hi;
- if ((pc_delta_hi >> 31) != 0 && (pc_delta_hi >> 31) != reg_t(-1) >> 31) {
- fprintf(stderr, "initial pc %" PRIx64 " out of range\n", pc_delta);
- abort();
- }
uint32_t reset_vec[reset_vec_size] = {
- 0x297 + uint32_t(pc_delta_hi), // auipc t0, &pc
- 0x597, // auipc a1, &dtb
- 0x58593 + ((reset_vec_size - 1) * 4 << 20), // addi a1, a1, &dtb
- 0xf1402573, // csrr a0, mhartid
- 0x28067 + uint32_t(pc_delta_lo << 20) // jalr zero, t0, &pc
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->xlen == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
};
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));