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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:47:13 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:47:13 -0700 |
| commit | 212d5198cfa79ac85a7b073c13cdf86e803614ee (patch) | |
| tree | 75ccb776665541cead24d3a367a335b0b424aa05 /riscv/sim.cc | |
| parent | 0647cce541357bf8f35c8930b78ae98b71ab1f02 (diff) | |
| download | spike-212d5198cfa79ac85a7b073c13cdf86e803614ee.zip spike-212d5198cfa79ac85a7b073c13cdf86e803614ee.tar.gz spike-212d5198cfa79ac85a7b073c13cdf86e803614ee.tar.bz2 | |
bootrom: set a0 to hartid and a1 to dtb before boot
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 445c17a..a2b5cd1 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -243,14 +243,14 @@ void sim_t::make_dtb() reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align; reg_t cpu_size = align; - uint32_t reset_vec[8] = { - 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector - 0x00028067, // jump straight to DRAM_BASE - 0x00000000, // reserved - 0, // config string pointer - 0, 0, 0, 0 // trap vector + uint32_t reset_vec[] = { + 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE + 0x597, // auipc a1, 0 + 0x58593, // addi a1, a1, 0 + 0xf1402573, // csrr a0,mhartid + 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE) }; - reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer + reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); |