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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 17:34:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
| commit | ce69fb5db97ecf240336b7826dd9dddeb32e5dca (patch) | |
| tree | f78647d0eafa9abc414f5ded2a3663c7506cfd9c /riscv/rocc.cc | |
| parent | a51e44ed228e48fc1dbf24ec7dc23cbd61a7874a (diff) | |
| download | spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.zip spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.gz spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.bz2 | |
Suppress most unused variable warnings
Diffstat (limited to 'riscv/rocc.cc')
| -rw-r--r-- | riscv/rocc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/rocc.cc b/riscv/rocc.cc index f50934f..f0dd0b2 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -18,7 +18,7 @@ return pc+4; \ } \ \ - reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \ + reg_t rocc_t::custom##n(rocc_insn_t UNUSED insn, reg_t UNUSED xs1, reg_t UNUSED xs2) \ { \ illegal_instruction(); \ return 0; \ |