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| author | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2013-10-15 00:21:00 -0700 |
|---|---|---|
| committer | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2013-10-15 00:21:00 -0700 |
| commit | 658188c92b337c85a472f6de8067518a2e95de7d (patch) | |
| tree | 1c1b28e51b69ea9ee599d9468229952ae1e5a522 /riscv/rocc.cc | |
| parent | 61d215fc61c66aaaed3e1aaa7f3cb45bfa71b58d (diff) | |
| download | spike-658188c92b337c85a472f6de8067518a2e95de7d.zip spike-658188c92b337c85a472f6de8067518a2e95de7d.tar.gz spike-658188c92b337c85a472f6de8067518a2e95de7d.tar.bz2 | |
Fix bug where xs2 was not being properly respected.
Diffstat (limited to 'riscv/rocc.cc')
| -rw-r--r-- | riscv/rocc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/rocc.cc b/riscv/rocc.cc index a4766d4..2354f9f 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -15,7 +15,7 @@ union rocc_insn_union_t rocc_insn_union_t u; \ u.i = insn; \ reg_t xs1 = u.r.xs1 ? RS1 : -1; \ - reg_t xs2 = u.r.xs1 ? RS2 : -1; \ + reg_t xs2 = u.r.xs2 ? RS2 : -1; \ reg_t xd = rocc->custom##n(u.r, xs1, xs2); \ if (u.r.xd) \ WRITE_RD(xd); \ |