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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-18 18:28:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-18 18:28:05 -0700 |
| commit | 01c01cc36f006cfb03cd6d1c5a68f926b93f7787 (patch) | |
| tree | 1bc5333057ff935073a595834092e4dd0936e34d /riscv/riscv.mk.in | |
| download | spike-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.zip spike-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.tar.gz spike-01c01cc36f006cfb03cd6d1c5a68f926b93f7787.tar.bz2 | |
Reorganized directory structure
Moved cross-compiler to /xcc/ rather than /
Added ISA sim in /sim/
Added Proxy Kernel in /pk/ (to be cleaned up)
Added opcode map to /opcodes/ (ditto)
Added documentation to /doc/
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in new file mode 100644 index 0000000..ada62d5 --- /dev/null +++ b/riscv/riscv.mk.in @@ -0,0 +1,23 @@ +riscv_subproject_deps = + +riscv_hdrs = \ + common.h \ + decode.h \ + execute.h \ + load_elf.h \ + mmu.h \ + processor.h \ + sim.h \ + trap.h \ + insns/*.h \ + +riscv_srcs = \ + load_elf.cc \ + processor.cc \ + sim.cc \ + trap.cc \ + +riscv_test_srcs = + +riscv_install_prog_srcs = \ + riscv-isa-run.cc \ |