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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-19 20:47:29 -0700 |
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| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-19 20:47:29 -0700 |
| commit | 77452a26e7d95d29dbaa797595ae683f03a3345b (patch) | |
| tree | e7aaae682f73a20ceb4d3366528b0cd38378f49d /riscv/riscv.mk.in | |
| parent | 740f981cfd55604d46598144dccac26dd53f643c (diff) | |
| download | spike-77452a26e7d95d29dbaa797595ae683f03a3345b.zip spike-77452a26e7d95d29dbaa797595ae683f03a3345b.tar.gz spike-77452a26e7d95d29dbaa797595ae683f03a3345b.tar.bz2 | |
temporary undoing of renaming
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in new file mode 100644 index 0000000..50dc76a --- /dev/null +++ b/riscv/riscv.mk.in @@ -0,0 +1,50 @@ +riscv_subproject_deps = \ + softfloat_riscv \ + softfloat \ + +riscv_hdrs = \ + htif.h \ + common.h \ + decode.h \ + mmu.h \ + processor.h \ + sim.h \ + trap.h \ + opcodes.h \ + insn_header.h \ + dispatch.h \ + +NDISPATCH := 10 +DISPATCH_SRCS := \ + dispatch0.cc \ + dispatch1.cc \ + dispatch2.cc \ + dispatch3.cc \ + dispatch4.cc \ + dispatch5.cc \ + dispatch6.cc \ + dispatch7.cc \ + dispatch8.cc \ + dispatch9.cc \ + dispatch10.cc \ + +$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs) + $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@ + +$(src_dir)/riscv/dispatch.h: %.h: dispatch + $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@ + +riscv_srcs = \ + htif.cc \ + processor.cc \ + sim.cc \ + interactive.cc \ + trap.cc \ + icsim.cc \ + mmu.cc \ + $(DISPATCH_SRCS) \ + +riscv_test_srcs = + +riscv_install_prog_srcs = \ + riscv-isa-run.cc \ |