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| author | Anup Patel <anup@brainfault.org> | 2021-12-14 11:25:55 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-04-20 10:20:10 +0530 |
| commit | 5a433081f4ce1a49ee83d1a81cf4922e7542a20c (patch) | |
| tree | c99dfe8db908caf9319c905e5bba388b3206d43a /riscv/riscv.mk.in | |
| parent | d5b1a65c0e3a0b6b46eb66d5d0284bf3a6cc1e0c (diff) | |
| download | spike-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.zip spike-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.tar.gz spike-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.tar.bz2 | |
Add PLIC emulation
We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.
The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 0c6b977..7f1fc9a 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -54,6 +54,7 @@ riscv_srcs = \ devices.cc \ rom.cc \ clint.cc \ + plic.cc \ debug_module.cc \ remote_bitbang.cc \ jtag_dtm.cc \ |