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| author | Andy Wright <acwright@mit.edu> | 2018-05-31 13:53:12 -0400 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-31 10:53:12 -0700 |
| commit | d6fcfdebf6a893bf37670fd67203d18653df4a0e (patch) | |
| tree | f4b65db4f03545a10815ec021a39b8aee64f8ffc /riscv/riscv.mk.in | |
| parent | 19efe7d1121ab0e1a3014a1554e7340fa958c13f (diff) | |
| download | spike-d6fcfdebf6a893bf37670fd67203d18653df4a0e.zip spike-d6fcfdebf6a893bf37670fd67203d18653df4a0e.tar.gz spike-d6fcfdebf6a893bf37670fd67203d18653df4a0e.tar.bz2 | |
Put simif_t declaration in its own file. (#209)
By separating the simif_t declaration from the sim_t declaration, the
simif_t declaration no longer depends on fesvr header files. This
simplifies compilation of custom sim class implementations that don't
depend on fesvr.
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 60c4403..80755e7 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -15,6 +15,7 @@ riscv_hdrs = \ mmu.h \ processor.h \ sim.h \ + simif.h \ trap.h \ encoding.h \ cachesim.h \ |