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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-11 16:13:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-11 16:13:59 -0700 |
| commit | e665e552b3944f4003f2cef76f650b38570cb854 (patch) | |
| tree | ffbc4fe09900afc8002d1fd4b4e858106e96c79a /riscv/riscv.ac | |
| parent | a23f18a6a6b647c7872e605662d8803b15a01e4d (diff) | |
| download | spike-e665e552b3944f4003f2cef76f650b38570cb854.zip spike-e665e552b3944f4003f2cef76f650b38570cb854.tar.gz spike-e665e552b3944f4003f2cef76f650b38570cb854.tar.bz2 | |
[xcc] fix configure scripts
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 897b21f..00358fd 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -8,8 +8,8 @@ AS_IF([test "x$enable_64bit" != "xno"], [ AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported]) ]) -AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression])) -AS_IF([test "x$enable_rvc" != "xno"], [ +AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression])) +AS_IF([test "x$enable_rvc" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) ]) @@ -18,7 +18,7 @@ AS_IF([test "x$enable_vec" != "xno"], [ AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) ]) -AC_ARG_ENABLE([icsim], AS_HELP_STRING([--disable-icsim], [Enable instruction cache simulator])) +AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator])) AS_IF([test "x$enable_icsim" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled]) ]) |