diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-08-01 23:13:37 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-08-02 00:05:49 -0700 |
| commit | b595bd3ab098cfa6753882f98a7136f12515e3cc (patch) | |
| tree | 1ce816d1659d2e09ab6bcdce33689f762aecf82e /riscv/riscv.ac | |
| parent | bd5dcc15383d002088a9e0b8b827660a4869cdaf (diff) | |
| download | spike-b595bd3ab098cfa6753882f98a7136f12515e3cc.zip spike-b595bd3ab098cfa6753882f98a7136f12515e3cc.tar.gz spike-b595bd3ab098cfa6753882f98a7136f12515e3cc.tar.bz2 | |
rvv: use formal way to generate --enable-1905-check
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 40cf706..213ba8d 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -38,3 +38,8 @@ AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardwa AS_IF([test "x$enable_misaligned" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores]) ]) + +AC_ARG_ENABLE([1905-check], AS_HELP_STRING([--enable-1905-check], [Enable 1905 release check])) +AS_IF([test "x$enable_1905_check" = "xyes"], [ + AC_DEFINE([RISCV_ENABLE_1950_CHECK],,[Enable 1905 release check]) +]) |